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AMD introduced its Spartan UltraScale+ programmable logic chips for edge applications.
The Santa Clara, California-based company unveiled its latest field programmable gate arrays (FPGAs), acquired through the purchase of Xilinx, designed specifically for cost-sensitive edge applications.
These advanced FPGAs offer high input/output (I/O) counts, power efficiency, and cutting-edge security features, catering to industries such as embedded vision, healthcare, industrial networking, robotics, and video applications.
Rob Bauer, senior manager of product marketing at AMD, highlighted the significance of this new FPGA line, emphasizing its role in powering breakthrough advances in various industries.
The Spartan UltraScale+ devices mark a significant advancement in FPGA technology, boasting industry-leading I/O to logic cell ratios, lower power consumption, and improved performance compared to previous generations.
Kirk Saban, corporate vice president in the Adaptive and Embedded Computing Group at AMD, praised the Spartan UltraScale+ family for modernizing features, design tools, and ensuring long product lifecycles.
Flexible I/O and power efficiency
The Spartan UltraScale+ FPGAs are optimized for edge computing, providing high I/O counts and flexible interfaces for seamless integration with multiple devices or systems.
With attributes like reduced power consumption, support for different packaging sizes, and security features like Post-Quantum Cryptography, the Spartan UltraScale+ family ensures a balance of power efficiency and future-ready capabilities.
AMD’s commitment to security in edge applications is evident through features like PPK/SPK key support, differential power analysis protection, and enhanced single-event upset performance to enhance device security.
The entire AMD FPGA portfolio, including the Spartan UltraScale+ family, is well-supported by the AMD Vivado Design Suite and Vitis Unified Software Platform, enabling designers to leverage tools and IPs effectively.
The Spartan UltraScale+ FPGA family is set to be available for sampling and evaluation in the first half of 2025, with tool support expected to follow later in 2024.
